1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and, more particularly, to a semiconductor memory device that can perform a highly reliable data read operation at a high speed.
2. Description of the Related Art
As a semiconductor memory device that reads data by comparing a memory cell with a read reference cell, there is a nonvolatile semiconductor memory device that stores data utilizing differences in threshold voltage.
In a stacked-gate nonvolatile semiconductor memory device such as a flash memory, for instance, data is stored utilizing variations in threshold voltage depending on the number of electrons in a floating gate. In such a case, the threshold voltage is set as follows.
In a case of memory cells that store digital data, the threshold voltage of the memory cells that constitute a memory cell array is set within one of two threshold voltage ranges. The threshold voltage of a memory cell that stores “1” is lower than a first threshold voltage. The threshold voltage of a memory cell that stores “0” is higher than a second threshold voltage. Here, the first threshold voltage is lower than the second threshold voltage. Meanwhile, the threshold voltage of a read reference cell is set between the first and second threshold voltages in advance.
The difference between the threshold voltage of the reference cell and the threshold voltage of a memory cell that stores “1” or “0” serves as a threshold voltage margin (hereinafter referred to as “read margin”) for reading the data “1” or “0”. The above relationship between threshold voltages also holds in a semiconductor memory device that stores multilevel data in memory cells.
Next, a data reading method in which data is read in accordance with the difference between the threshold voltages of the reference cell and a memory cell will be described. Cell currents flowing through the memory cell and the reference cell are converted into voltages, and a comparator circuit 11 then compares the voltages. As shown in FIG. 1, a comparison result signal RS depending on the relationship between the threshold voltages of the reference cell and the memory cell is obtained. In accordance with the comparison result signal RS, it is determined whether the read data is “1” or “0”. In this method, it is essential to make the comparison with the conditions of the gates, the drains, the sources, and the back biases being all equalized between the reference cell and the memory cell to be read.
Meanwhile, as portable information devices have become widely spread in recent years, there has been an increasing demand for nonvolatile semiconductor memory devices that performs at lower voltages. To achieve a low voltage operation, the word line is boosted so as to increase the cell current difference between the reference cell and a memory cell from which data is read out. The boosting is performed at the start of a read operation so as to reduce the standby current of the nonvolatile semiconductor memory device. Likewise, the biasing of the bit line is performed only during a data read operation, and no biasing is performed while standing by.
The timings of boosting the word line and biasing the bit line are controlled by a timing circuit.
However, since the distance between a memory cell and a word line driver or a bit line bias circuit varies depending on the location of the memory cell, there is a difference in signal transmission time among memory cells. As a result, at the early stage of a data read operation, differences are also caused to the bias conditions of the gates and drains. To solve this problem, a sufficient time is maintained so as to make uniform the bias conditions between the gate and drain of a memory cell prior to the cell current comparison between the reference cell and the memory cell. However, this is a hindrance to a high-speed read operation.
In a case where no extra time is ensured before the cell current comparison so as to perform a high-speed read operation, on the other hand, there is a problem that the read margin is reduced. Since the read margin depends on the location of each memory cell, problems (described later) might arise.
FIG. 1 shows the structure of a conventional nonvolatile semiconductor memory device. This nonvolatile semiconductor memory device comprises a timing circuit 1, a word line driver 3, a bit line decoder 5, a reference word line driver 7, cascode-type sense circuits 9 and 10, the comparator circuit 11, dummy cells 12, memory cells MC0 to MCn, a reference cell RC, a word line WL, a reference word line RWL, bit lines BL0 to BLn, and a reference bit line RBL.
The word line driver 3 and the reference word line driver 7 are connected to the timing circuit 1, and drive the word line WL and the reference word line RWL, respectively. A booster power voltage VPP is supplied to the word line driver 3 and the reference word line driver 7. An activation signal AS for activating each driver is supplied from the timing circuit 1. The word line driver 3 selects the word line WL for activation, in accordance with a select signal SS.
The gate of each of the memory cells MC0 to MCn is connected to the word line WL, while the source is grounded. The bit lines BL0 to BLn are selectively activated by the bit line decoder 5, in accordance with column address signals CA0 and CA1 and their inversion signals CA0B and CA1B. The bit line decoder 5 will be described later in greater detail.
Like the memory cells MC0 to MCn, the gate of the reference cell RC is connected to the reference word line RWL, while the source is grounded. The drain of the reference cell RC is connected to the reference bit line RBL. The dummy cells 12 as the equivalents of the memory cells MC0 to MC(n−1) are also connected to the reference word line RWL.
The cascode sense circuit 9 is connected to the bit line decoder 5, and the cascode sense circuit 10 is connected to the reference bit line RBL. The cascode sense circuits 9 and 10 will be described later in greater detail. The comparator circuit 11 is connected to the cascode sense circuits 9 and 10.
FIG. 2 is a circuit diagram showing the structure of the bit line decoder 5. In this example shown in FIG. 2, four memory cells MC0 to MC3 are connected to the word line WL. As shown in FIG. 2, n-channel MOS transistors NT7 and NT8 are connected in series to the bit line BL0. The column address signal CA0B is supplied to the gate of the n-channel MOS transistor NT7, while the column address signal CA1B is supplied to the gate of the n-channel MOS transistor NT8.
In parallel with the n-channel MOS transistor NT7, an n-channel MOS transistor NT9 is connected to the bit line BL1, and the column address signal CA0 is supplied to the gate of the n-channel MOS transistor NT9.
Likewise, n-channel MOS transistors NT10 and NT11 are connected in series to the bit line BL2. The column address signal CA0B is supplied to the gate of the n-channel MOS transistor NT10, while the column address signal CA1 is supplied to the gate of the n-channel MOS transistor NT11. In parallel with the n-channel MOS transistor NT10, an n-channel MOS transistor NT12 is connected to the bit line BL3, and the column address signal CA0 is supplied to the gate of the n-channel MOS transistor NT12.
The bit line decoder 5 having the above structure operates in the following manner. When high-level column address signals CA0B and CA1B are supplied to the bit line decoder 5, the bit line BL0 is activated, and data DATAB is read out from the memory cell MC0.
When high-level column address signals CA0 and CA1B are supplied to the bit line decoder 5, the bit line BL1 is activated, and the data DATAB is read out from the memory cell MC1. When high-level column address signals CA0B and CA1 are supplied to the bit line decoder 5, the bit line BL2 is activated, and the data DATAB is read out from the memory cell MC2. When high-level column address signals CA0 and CA1 are supplied to the bit line decoder 5, the bit line BL3 is activated, and the data DATAB is read out from the memory cell MC3.
FIG. 3 is a circuit diagram showing the structure of the cascode sense circuit 10 shown in FIG. 1. As shown in FIG. 3, this cascode sense circuit 10 comprises a load 13, n-channel MOS transistors NT1 to NT3, and an inversion circuit INV. Here, the load 13 is connected to a node that supplies a power voltage VDD, and the n-channel MOS transistors NT1 to NT3 are connected in series to the load 13. The n-channel transistor NT3 is connected to the reference cell RC. The input node of the inversion circuit INV is connected to the source of the n-channel MOS transistor NT1, while the output mode of the inversion circuit INV is connected to the gate of the n-channel MOS transistor NT1.
In the cascode sense circuit 10 having the above structure, the drain of the n-channel MOS transistor NT1 is connected to the comparator circuit 11, so that a signal SAREF corresponding to the data DATAB read out from the reference cell RC is supplied to the comparator circuit 11. In other words, this cascode sense circuit 10 generates the signal SAREF having a voltage corresponding to a cell current flowing through the reference cell RC, and supplies the signal SAREF to the comparator circuit 11.
The cascode sense circuit 9 has the same structure as the cascode sense circuit 10, generating a signal SAI that has a voltage depending on a cell current flowing through a selected memory cell. The generated signal SAI is also supplied to the comparator circuit 11.
In the conventional nonvolatile semiconductor memory device having the above structure, a first distance between a selected one of the memory cells MC0 to MCn to be read and the word line driver 3 on the word line WL differs from a second distance between the reference cell RC and the reference word line driver 7 on the reference word line RWL. Because of this difference between the first distance and the second distance, there might be times that a sufficient read margin cannot be maintained. For instance, if the memory cell MCn is selected to be an object to be read, the first distance and the second distance are almost the same. If the memory cell MC0 is selected, the first distance becomes much shorter than the second distance.
Referring now to FIG. 4, the influence that the locations of the cells have on the read margin will be described below. FIG. 4 is a graph in which the abscissa axis shows the time while the ordinate axis shows the voltage. This graph shows a gate voltage V0g of the memory cell MC0, a gate voltage Vng of the memory cell MCn, signals SAI0(0) and SAI0(1) corresponding to the data “0” and “1” read from the memory cell MC0, signals SAIn(0) and SAIn(1) corresponding to the data “0” and “1” read from the memory cell MCn, and the signal SAREF supplied from the cascode sense circuit 10 to the comparator circuit 11.
When the word line driver 3 activates the word line WL, the gate voltage Vng of the memory cell MCn is delayed with respect to the gate voltage V0g of the memory cell MC0, and then increased. The waveforms of the signals SAI(0) and SAI(1) corresponding to the data “0” and “1” read from the memory cells vary with the locations of the memory cells. For instance, the signal SAI0(0) corresponding to the data “0” read from the memory cell MC0 has a smaller value than the signal SAREF prior to the time t0, and as a result, the data “0” cannot be read out properly.
When the data “0” is read from the memory cell MC0, in order to maintain the same read margin as in the case of reading the data from the memory cell MCn, the comparator circuit 11 needs to determine whether the data is “0” or “1” after the time t1 shown in FIG. 4. This becomes a hindrance to a high-speed operation.